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CAT34TS02
Digital Output Temperature Sensor with On-board SPD EEPROM
FEATURES
JEDEC JC42.4 Compliant Temperature Sensor Temperature Range: - 40C to +125C DDR3 DIMM compliant SPD EEPROM Supply Range: 3.3 V 10% I C / SMBus Interface Schmitt Triggers and Noise Suppression Filters on SCL and SDA Inputs Low Power CMOS Technology RoHS-compliant 2 x 3 x 0.75 mm TDFN package
2
DESCRIPTION
The CAT34TS02 combines a JC42.4 compliant Temperature Sensor (TS) with 2-Kb of Serial Presence Detect (SPD) EEPROM. The TS measures temperature at least 10 times every second. Temperature readings can be retrieved by the host via the serial interface, and are compared to high, low and critical trigger limits stored into internal registers. Over or under limit conditions can be signaled on the open-drain EVENT pin. The integrated 2-Kb SPD EEPROM is internally organized as 16 pages of 16 bytes each, for a total of 256 bytes. It features a 16-byte page write buffer and supports both the Standard (100 kHz) as well as Fast 2 (400 kHz) I C protocol. Write operations to the lower half memory can be inhibited via software commands. The CAT34TS02 features Permanent, as well as Reversible Software Write Protection, as defined for DDR3 DIMMs.
For Ordering Information details, see page 21.
PIN CONFIGURATION
TDFN (VP2)
(2 x 3 x 0.75 mm)
A0 1 A1 2
A2 3 VSS 4
8 VCC 7 EVENT 6 SCL 5 SDA
FUNCTIONAL SYMBOL
VCC
Note: For the location of Pin 1, please consult the corresponding package drawing.
SCL
PIN FUNCTIONS
Name A0, A1, A2 SDA SCL EVENT VCC VSS DAP Description Device Address Input Serial Data Input/Output Serial Clock Input Open-drain Event Output Power Supply Ground Backside exposed DAP at VSS
A2, A1, A0
SDA
CAT34TS02
EVENT
VSS
(c) 2010 SCILLC. All rights reserved. Characteristics subject to change without notice
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Doc. No. MD-1129 Rev. G
CAT34TS02
Absolute Maximum Ratings
(1)
Parameter Operating Temperature Storage Temperature (2) Voltage on any pin (except A0) with respect to Ground Voltage on pin A0 with respect to Ground RELIABILITY CHARACTERISTICS Symbol (4) NEND TDR
(3)
Rating -45 to +130 -65 to +150 -0.5 to +6.5 -0.5 to +10.5
Units C C V V
Parameter Endurance (EEPROM) Data Retention (EEPROM)
Min 1,000,000 100
Units Write Cycles Years
TEMPERATURE CHARACTERISTICS VCC = 3.3 V 10%, TA = -40C to +125C, unless otherwise specified Parameter Temperature Reading Error Class B, JC42.4 compliant ADC Resolution Temperature Resolution Conversion Time Thermal Resistance JA
(3)
Test Conditions/Comments +75C TA +95C, active range +40C TA +125C, monitor range -40C TA +125C, sensing range
Max 1.0 2.0 3.0 12 0.0625 100
Unit C C C Bits C ms C/W
Junction-to-Ambient (Still Air)
92
D.C. OPERATING CHARACTERISTICS VCC = 3.3 V 10%, TA = -40C to +125C, unless otherwise specified Symbol ICC ISHDN ILKG VIL VIH VOL1 VOL2 Parameter Supply Current Standby Current I/O Pin Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage IOL = 3 mA, VCC > 2.7 V IOL = 1 mA, VCC < 2.7 V Test Conditions/Comments TS active, SPD and Bus idle EEPROM Write, TS shut-down TS shut-down; SPD and Bus idle Pin at GND or VCC -0.5 0.7 x VCC Min Max 500 500 10 2 0.3 x VCC VCC + 0.5 0.4 0.2 Unit A A A A V V V V
Notes: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. The A0 pin can be raised to a HV level for RSWP command execution. SCL and SDA inputs can be raised to the maximum limit, irrespective of VCC. (3) Power Dissipation is defined as PJ = (TJ - TA)/JA, where TJ is the junction temperature and TA is the ambient temperature. The thermal resistance value refers to the case of a package being used on a standard 2-layer PCB. (4) Page Mode, VCC = 3.3 V, 25C
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(c) 2010 SCILLC. All rights reserved. Characteristics subject to change without notice
CAT34TS02
A.C. CHARACTERISTICS
(1)
VCC = 3.3 V 10%, TA = -40C to +125C Symbol
(2) FSCL
Parameter Clock Frequency High Period of SCL Clock Low Period of SCL Clock
Min 10 600 1300 25
Max 400
Units kHz ns ns
tHIGH tLOW tTIMEOUT tR tF
(3) (3) (2)
SMBus SCL Clock Low Timeout SDA and SCL Rise Time SDA and SCL Fall Time Data Setup Time Data Hold Time (for Input Data) Data Hold Time (for Output Data) START Condition Setup Time START Condition Hold Time STOP Condition Setup Time Bus Free Time Between STOP and START Noise Pulse Filtered at SCL and SDA Inputs Write Cycle Time Power-up Delay to Valid Temperature Recording
35 300 300
ms ns ns ns ns
(4) tSU:DAT
100 0 300 600 600 600 1300 100 5 100 900
tHD:DAT
(3)
ns ns ns ns ns ns ms ms
tSU:STA tHD:STA tSU:STO tBUF Ti tWR
(5) tPU
PIN CAPACITANCE TA = 25C, VCC = 3.3 V, f = 1 MHz Symbol CIN Parameter SDA, EVENT Pin Capacitance Input Capacitance (other pins) Test Conditions/Comments VIN = 0 VIN = 0 Min Max 8 6 Unit pF pF
Notes: (1) Timing reference points are set at 30%, respectively 70% of VCC, as illustrated in Figure 4. Bus loading must be such as to allow meeting the VIL, VOL as well as the various timing limits. (2) The TS interface will reset itself and will release the SDA line if the SCL line stays low beyond the tTIMEOUT limit. The time-out count is started (and then re-started) on every negative transition of SCL in the time interval between START and STOP. The minimum clock frequency of 10 kHz is an SMBus recommendation; the minimum operating clock frequency for the CAT34TS02's SPD component is DC, while the minimum operating frequency for the TS component is limited only by the SMBus time-out. In a "Wired-OR" system (such as I2C or SMBus), SDA rise time is determined by bus loading. Since each bus pull-down device must be able to sink the (external) bus pull-up current (in order to meet the VIL and/or VOL limits), it follows that SDA fall time is inherently faster than SDA rise time. SDA rise time can exceed the standard recommended tR limit, as long as it does not exceed tLOW - tHD:DAT - tSU:DAT, where tLOW and tHD:DAT are actual values (rather than spec limits). A shorter tHD:DAT leaves more room for a longer SDA tR, allowing for a more capacitive bus or a larger bus pull-up resistor. At the minimum tLOW spec limit of 1300 ns, the maximum tHD:DAT of 900 ns demands a maximum SDA tR of 300 ns. The CAT34TS02's maximum tHD:DAT is <700 ns, thus allowing for an SDA tR of up to 500 ns at minimum tLOW. The minimum tSU:DAT of 100 ns is a limit recommended by standards. The CAT34TS02 will accept a tSU:DAT of 0 ns. The first valid temperature recording can be expected after tPU at nominal supply voltage. 3
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(3)
(4) (5)
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CAT34TS02
TYPICAL PERFORMANCE CHARACTERISTICS VCC = 3.3 V, TA = -25C to +125C, unless otherwise specified. TS Active Current
(IC-bus and SPD EEPROM idle)
300 250 200
7 6 5
Standby Current
(IC-bus and SPD EEPROM idle, TS shut-down)
ICC (A)
ISHDN (A)
-25 0 25 50 75 100 125
150 100 50
4 3 2 1
0
0 -50 -25 0 25 50 75 100 125 150
TAMB (C)
TAMB (C)
SPD EEPROM Write Current
(IC-bus idle, TS shut-down)
4 500 3 2 400
Temperature Read-Out Error
ICC_WR (A)
T (C)
1 0 -1 -2
Part # 2
300
Part # 1
200
-3 -4
100 -25 0 25 50 75 100 125
-25
0
25
50
75
100
125
TAMB (C)
TAMB (C)
A/D Conversion Time
80 70 5 4.5 4
EEPROM Write Time
TCONV (ms)
60 50 40 30 20 -25 0 25 50 75 100 125
tWR (ms)
3.5 3 2.5 2 -25 0 25 50 75 100 125
TAMB (C)
TAMB (C)
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(c) 2010 SCILLC. All rights reserved. Characteristics subject to change without notice
CAT34TS02
TYPICAL PERFORMANCE CHARACTERISTICS VCC = 3.3 V, TA = -25C to +125C, unless otherwise specified. TS POR Threshold Voltage
3.00
2.60
VTH (V)
2.20
1.80
1.40
1.00 -25 0 25 50 TAMB (C) 75 100 125
SPD POR Threshold Voltage
2.00
1.80
VTH (V)
1.60
1.40
1.20
1.00 -25 0 25 50 75 100 125
TAMB (C)
SMBus SCL Clock Low Timeout
40
35
tTIMEOUT (ms)
30
25
20 -25 0 25 50 75 100 125
TAMB (C)
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Doc. No. MD-1129 Rev. G
CAT34TS02 PIN DESCRIPTION
SCL: The Serial Clock input pin accepts the Serial Clock generated by the Master (Host). SDA: The Serial Data I/O pin receives input data and transmits data stored in the internal registers. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL. A0, A1 and A2: The Address pins accept the device address. These pins have on-chip pull-down resistors. EVENT: The open-drain EVENT pin can be programmed to signal over/under temperature limit conditions.
I2C/SMBUS PROTOCOL
The I C/SMBus uses two `wires', one for clock (SCL) and one for data (SDA). The two wires are connected to the VCC supply via pull-up resistors. Master and Slave devices connect to the bus via their respective SCL and SDA pins. The transmitting device pulls down the SDA line to `transmit' a `0' and releases it to `transmit' a `1'. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, the SDA line must remain stable while the SCL line is HIGH. An SDA transition while SCL is HIGH will be interpreted as a START or STOP condition (Figure 1). START The START condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START acts as a `wake-up' call to all Slaves. Absent a START, a Slave will not respond to commands. STOP The STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while SCL is HIGH. The STOP tells the Slave that no more data will be written to or read from the Slave. DEVICE ADDRESSING The Master initiates data transfer by creating a START condition on the bus. The Master then broadcasts an 8-bit serial Slave address. The first 4 bits of the Slave address (the preamble) select either the Temperature Sensor (TS) registers (0011) or the EEPROM memory contents (1010), as shown in Figure 2. The next 3 bits, A2, A1 and A0, select one of 8 possible Slave devices. The last bit, R/W , specifies whether a Read (1) or Write (0) operation is being performed ACKNOWLEDGE A matching Slave address is acknowledged (ACK) by the Slave by pulling down the SDA line during the th 9 clock cycle (Figure 3). After that, the Slave will acknowledge all data bytes sent to the bus by the Master. When the Slave is the transmitter, the th Master will in turn acknowledge data bytes in the 9 clock cycle. The Slave will stop transmitting after the Master does not respond with acknowledge (NoACK) and then issues a STOP. Bus timing is illustrated in Figure 4.
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POWER-ON RESET (POR)
The CAT34TS02 incorporates Power-On Reset (POR) circuitry which protects the device against powering up to invalid state. The TS component will power up into conversion mode after VCC exceeds the TS POR trigger level and the SPD component will power up into standby mode after VCC exceeds the SPD POR trigger level. Both the TS and SPD components will power down into Reset mode when VCC drops below their respective POR trigger levels. This bi-directional POR behavior protects the CAT34TS02 against brown-out failure following a temporary loss of power. The POR trigger levels are set below the minimum operating VCC level.
DEVICE INTERFACE
The CAT34TS02 supports the Inter-Integrated 2 Circuit (I C) and the System Management Bus (SMBus) data transmission protocols. These protocols describe serial communication between transmitters and receivers sharing a 2-wire data bus. Data flow is controlled by a Ma ster device, which generates the serial clock and the START and STOP conditions. The CAT34TS02 acts as a Slave device. Master and Slave alternate as transmitter and receiver. Up to 8 CAT34TS02 devices may be present on the bus simultaneously, and can be individually addressed by matching the logic state of the address inputs A0, A1, and A2.
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(c) 2010 SCILLC. All rights reserved. Characteristics subject to change without notice
CAT34TS02
Figure 1. Start/Stop Timing
SDA
SCL START BIT STOP BIT
Figure 2. Slave Address Bits
EEPROM
1
0
1
0
A2
A1
A0
R/W
TEMPERATURE SENSOR
0
0
1
1
A2
A1
A0
R/W
PREAMBLE
DEVICE ADDRESS
Figure 3. Acknowledge Timing
SCL FROM MASTER
1
8
9
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE
Figure 4. Bus Timing
tF tLOW SCL
70% 70% 30%
tHIGH
70% 30%
tR
70%
tSU:STA tHD:STA SDA
70% 30%
tHD:DAT tSU:DAT
70% 30% 30%
tSU:STO
70% 70%
tBUF
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Doc. No. MD-1129 Rev. G
CAT34TS02 WRITE OPERATIONS
EEPROM Byte and TS Register Write To write data to a TS register, or to the on-board EEPROM, the Master creates a START condition on the bus, and then sends out the appropriate Slave address (with the R/W bit set to `0'), followed by an address byte and data byte(s). The matching Slave will acknowledge the Slave address, EEPROM byte or TS register address and the data byte(s), one for EEPROM data (Figure 5) and two for TS register data (Figure 6). The Master then ends the session by creating a STOP condition on the bus. The STOP completes the (volatile) TS register update or starts the internal Write cycle for the (non-volatle) EEPROM data (Figure 7). EEPROM Page Write The on-board EEPROM contains 256 bytes of data, arranged in 16 pages of 16 bytes each. A page is selected by the 4 most significant bits of the address byte immediatelly following the Slave address, while the 4 least significant bits point to the byte within the page. Up to 16 bytes can be written in one Write cycle (Figure 8). The internal EEPROM byte address counter is automatically incremented after each data byte is loaded. If the Master transmits more than 16 data bytes, then earlier data will be overwritten by later data in a `wrap-around' fashion within the selected page. The internal Write cycle, using the most recently loaded data, then starts immediatelly following the STOP. Acknowledge Polling Acknowledge polling can be used to determine if the CAT34TS02 is busy writing to EEPROM, or is ready to accept commands. Polling is executed by interrogating the device with a `Selective Read' command (see READ OPERATIONS). The CAT34TS02 will not acknowlwdge the Slave address as long as internal EEPROM Write is in progress.
DELIVERY STATE
The CAT34TS02 is shipped `unprotected', i.e. neither Software Write Protection (SWP) flag is set. The entire 2-Kb memory is erased, i.e. all bytes are 0xFF.
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(c) 2010 SCILLC. All rights reserved. Characteristics subject to change without notice
CAT34TS02
Figure 5. EEPROM Byte Write
BUS ACTIVITY: MASTER SDA LINE SLAVE S T A R T S A C K A C K A C K SPD SLAVE ADDRESS S T O P P
BYTE ADDRESS
DATA
Figure 6. Temperature Sensor Register Write
BUS ACTIVITY: MASTER SDA LINE SLAVE S T A R T S A C K A C K A C K A C K TS SLAVE ADDRESS S T O P P
REGISTER ADDRESS
DATA (MSB)
DATA (LSB)
Figure 7. EEPROM Write Cycle Timing
SCL
SDA
8th Bit Byte n
ACK tWR STOP CONDITION START CONDITION ADDRESS
Figure 8. EEPROM Page Write
BUS ACTIVITY: MASTER SDA LINE SLAVE
S T A R T S
SPD SLAVE ADDRESS
BYTE ADDRESS (n)
DATA n
DATA n+1
DATA n+P
S T O P P
A C K
A C K
A C K
A C K
A C K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
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Doc. No. MD-1129 Rev. G
CAT34TS02 READ OPERATIONS
Immediate Read Upon power-up, the address counters for both the Temperature Sensor (TS) and on-board EEPROM are initialized to 00h. The TS address counter will thus point to the Capability Register and the EEPROM address counter will point to the first location in memory. The two address counters may be updated by subsequent operations. A CAT34TS02 presented with a Slave address containing a `1' in the R/W position will acknowledge the Slave address and will then start transmitting data being pointed at by the current EEPROM data or respectively TS register address counter. The Master stops this transmission by responding with NoACK, followed by a STOP (Figure 9). Selective Read The Read operation can be started at an address different from the one stored in the respective address counters, by preceeding the Immediate Read sequence with a `data less' Write operation. The Master sends out a START, Slave address and address byte, but rather than following up with data (as in a Write operation), the Master then issues another START and continuous with an Immediate Read sequence (Figure 10). Sequential EEPROM Read EEPROM data can be read out indefinitely, as long as the Master responds with ACK (Figure 11). The internal address count is automatically incremented after every data byte sent to the bus. If the end of memory is reached during continuous Read, then the address counter `wraps-around' to beginning of memory, etc. Sequential Read works with either Immediate Read or Selective Read, the only difference being that in the latter case the starting address is intentionally updated.
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(c) 2010 SCILLC. All rights reserved. Characteristics subject to change without notice
CAT34TS02
Figure 9. Immediate Read
BUS ACTIVITY: MASTER SDA LINE SLAVE S T A R T S A C K DATA SPD SLAVE ADDRESS N OS AT CO KP P
BUS ACTIVITY: MASTER SDA LINE SLAVE
S T A R T S
TS SLAVE ADDRESS
A C K
N OS AT CO KP P
A C K
DATA (MSB)
DATA (LSB)
Figure 10. Selective Read
BUS ACTIVITY: MASTER SDA LINE SLAVE S T A R T S A C K A C K SPD SLAVE ADDRESS S T A R T S A C K DATA n N OS AT CO KP P
BYTE ADDRESS (n)
SLAVE ADDRESS
BUS ACTIVITY: MASTER SDA LINE SLAVE
S T A R T S
TS SLAVE ADDRESS
REGISTER ADDRESS
S T A R T S
SLAVE ADDRESS
A C K
N OS AT CO KP P
A C K
A C K
A C K
DATA (MSB)
DATA (LSB)
Figure 11. EEPROM Sequential Read
BUS ACTIVITY: MASTER SDA LINE SLAVE A C K DATA n DATA n+1 DATA n+2 DATA n+x SPD SLAVE ADDRESS N O A C K S T O P P
A C K
A C K
A C K
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Doc. No. MD-1129 Rev. G
CAT34TS02 SOFTWARE WRITE PROTECTION
The lower half of memory ( 128 bytes) can be first protected against Write requests by setting one of two Software Write Protection (SWP) flags. The Permanent Software Write Protection (PSWP) flag can be set or read while all address pins are at regular CMOS levels (GND or VCC), whereas the very high voltage VHV must be present on address pin A0 to set, clear or read the Reversible Software Write Protection (RSWP) flag. The D.C. OPERATING CONDITIONS for RSWP operations are shown in Table 1. The SWP commands are listed in Table 2. All commands are preceded by a START and terminated with a STOP, following the ACK or NoACK from the CAT34TS02. All SWP related Slave addresses use the pre-amble: 0110 (6h), instead of the regular 1010 (Ah) used for memory access. For PSWP commands, the three address pins can be at any logic level, whereas for RSWP commands the address pins must be at pre-assigned logic levels. VHV is interpreted as logic `1'. The VHV condition must be established on pin A0 before the START and maintained just beyond the STOP. Otherwise an RSWP request could be interpreted by the CAT34TS02 as a PSWP request. The SWP Slave addresses follow the standard I C convention, i.e. to read the state of the SWP flag, the LSB of the Slave address must be `1', and to set or clear a flag, it must be `0'. For Write commands a dummy byte address and dummy data byte must be provided (Figure 12). In contrast to a regular memory Read, a SWP Read does not return Data. Instead the CAT34TS02 will respond with NoACK if theflag is set and with ACK if the is not set. Therefore, the flag Master can immediately follow up with a STOP, as there is no meaningful data following the ACK interval (Figure 13).
2
Table 1: RSWP D.C. Operation Condition Symbol VHV IHVD VHV Parameter A0 Overdrive (VHV - VCC) A0 High Voltage Detector Current A0 Very High Voltage 1.7 V < VCC < 3.6 V 7 Test Conditions Min 4.8 0.1 10 Max Units V mA V
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CAT34TS02
Table 2. SWP Commands
Action A2 A2 Set PSWP A2 A2 GND Set RSWP GND GND GND GND Clear RSWP GND GND Control Pin Levels (1) A1 A1 A1 A1 GND GND GND GND VCC VCC VCC A0 A0 A0 A0 VHV VHV VHV VHV VHV VHV VHV Flag State(2) PSWP 1 0 0 1 0 0 0 1 0 0 RSWP X X X X 1 0 0 X X X 0110 b7 to b4 Slave Address b3 A2 A2 A2 0 0 0 0 0 0 0 b2 A1 A1 A1 0 0 0 0 1 1 1 b1 A0 A0 A0 1 1 1 1 1 1 1 b0 X 0 1 X X 0 1 X 0 1 ACK ? No Yes Yes No No Yes Yes No Yes Yes X Yes X Yes Yes X Yes X Yes Yes X Yes X Yes Yes Address Byte ACK ? Data Byte ACK ? Write Cycle
Figure 12. Software Write Protect (Write)
S T A R T S A C K X = Don't Care S T O P P
BUS ACTIVITY: MASTER SDA LINE SLAVE
SLAVE ADDRESS
BYTE ADDRESS XXXXXXXX A C K
DATA XXXXXXXX
N A C or O A K C K
Figure 13. Software Write Protect (Read)
BUS ACTIVITY: MASTER SDA LINE SLAVE
S T A R T S
SLAVE ADDRESS
S T O P P N A C or O A K C K
Notes: (1) Here A2, A1 and A0 are either at VCC or GND. (2) 1 stands for `Set', 0 stands for `Not Set', X stands for `don't care'.
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Doc. No. MD-1129 Rev. G
CAT34TS02 TEMPERATURE SENSOR OPERATION
The TS component in the CAT34TS02 combines a Proportional to Absolute Temperature (PTAT) sensor with a - modulator, yielding a 12 bit plus sign digital temperature representation. The TS runs on an internal clock, and starts a new conversion cycle at least every 100 ms. The result of the most recent conversion is stored in the Temperature Data Register (TDR), and remains there following a TS Shut-Down. Reading from the TDR does not interfere with the conversion cycle. The value stored in the TDR is compared against limits stored in the High Limit Register (HLR), the Low Limit Register (LLR) and/or Critical Temperature Register (CTR). If the measured value is outside the alarm limits or above the critical limit, then the EVENT pin may be asserted. The EVENT output function is programmable, via the Configuration Register for interrupt mode, comparator mode and polarity. The temperature limit registers can be Read or Written by the host, via the serial interface. At power-on, all the (writable) internal registers default to 0x0000, and should therefore be initialized by the host to the desired values.The EVENT output starts out disabled (corresponding to polarity active low); thus preventing irrelevant event bus activity before the limit registers are initialized. While the TS is enabled (not shut-down), event conditions are normally generated by a change in measured temperature as recorded in the TDR, but limit changes can also trigger events as soon as the new limit creates an event condition, i.e. asynchronously with the temperature sampling activity. In order to minimize the thermal resistance between sensor and PCB, it is recommended that the exposed backside die attach pad (DAP) be soldered to the PCB ground plane.
REGISTERS
The CAT34TS02 contains eight 16-bit wide registers allocated to TS functions, as shown in Table 3. Upon power-up, the internal address counter points to the capability register. Capability Register (User Read Only) This register lists the capabilities of the TS, as detailed in the corresponding bit map. Configuration Register (Read/Write) This register controls the various operating modes of the TS, as detailed in the corresponding bit map. Temperature Trip Point Registers (Read/Write) The CAT34TS02 features 3 temperature limit registers, the HLR, LLR and CLR mentioned earlier. The temperature value recorded in the TDR is compared to the various limit values, and the result is used to activate the EVENT pin. To avoid undesirable EVENT pin activity, this pin is automatically disabled at power-up to allow the host to initialize the limit registers and the converter to complete the first conversion cycle under nominal supply conditions. Data format is two's complement with the LSB representing 0.25C, as detailed in the corresponding bit maps. Temperature Data Register (User Read Only) This register stores the measured temperature, as well as trip status information. B15, B14, and B13 are the trip status bits, representing the relationship between measured temperature and the 3 limit values; these bits are not affected by EVENT status or by Configuration register settings. Measured temperature is represented by bits B12 to B0. Data format is two's complement, where B12 represents the sign, B11 represents 128C, etc. and B0 represents 0.0625C. Manufacturer ID Register (Read Only) The manufacturer ID assigned by the PCI-SIG trade organization to the CAT34TS02 device is fixed at 0x1B09. Device ID and Revision Register (Read Only) This register contains manufacturer specific device ID and device revision information.
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(c) 2010 SCILLC. All rights reserved. Characteristics subject to change without notice
CAT34TS02
Table 3: The TS Registers Register Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 Register Name Capability Register Configuration Register High Limit Register Low Limit Register Critical Limit Register Temperature Data Register Manufacturer ID Register Device ID/Revision Register Power-On Default 0x007F 0x0000 0x0000 0x0000 0x0000 Undefined 0x1B09 0x0813 Read/Write Read Read/Write Read/Write Read/Write Read/Write Read Read Read
CAPABILITY REGISTER B15 RFU B7 EVSD B14 RFU B6 TMOUT B13 RFU B5 RFU B12 RFU B4 B11 RFU B3 B10 RFU B2 RANGE B9 RFU B1 ACC B8 RFU B0 EVENT
TRES [1:0]
Bit B15:B8
Description Reserved for future use; can not be written; should be ignored; will read as 0 0: Configuration Register bit 4 is frozen upon Configuration Register bit 8 being set (i.e. a TS shut-down freezes the EVENT output) 1: Configuration Register bit 4 is cleared upon Configuration Register bit 8 being set (i.e. a TS shut-down de-asserts the EVENT output) 0: The TS implements SMBus time-out within the range 10 to 60 ms 1: The TS implements SMBus time-out within the range 25 to 35 ms 0: 1: 00: 01: 10: 11: Pin A0 VHV compliance required for RSWP Write/Clear operations not explicitly stated Pin A0 VHV compliance required for RSWP Write/Clear operations explicitly stated LSB = 0.50C (9 bit resolution) LSB = 0.25C (10 bit) LSB = 0.125C (11 bit) LSB = 0.0625C (12 bit)
B7
(1)
B6 B5
B4:B3
B2 B1 B0
0: Positive Temperature Only 1: Positive and Negative Temperature 0: 2C over the active range and 3C over the operating range (Class C) 1: 1C over the active range and 2C over the monitor range (Class B) 0: Critical Temperature only 1: Alarm and Critical Temperature
Notes: (1) Configuration Register bit 4 can be cleared (but not set) after Configuration Register bit 8 is set, by writing a "1" to Configuration Register bit 5 (EVENT output can be de-asserted during TS shut-down periods) 15
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Doc. No. MD-1129 Rev. G
CAT34TS02
CONFIGURATION REGISTER B15
RFU
B14
RFU
B13
RFU
B12
RFU
B11
RFU
B10
HYST [1:0]
B9 B1
B8
SHDN
B7
B6
B5
CLEAR
B4
EVENT_STS
B3
B2
B0
EVENT_MODE
TCRIT_LOCK EVENT_LOCK
EVENT_CTRL TCRIT_ONLY EVENT_POL
Bit B15:B11 B10:B9
(1)
Description Reserved for future use ; can not be written ; should be ignored; will read as 0 00: Disable hysteresis 01: Set hysteresis at 1.5C 10: Set hysteresis at 3C 11: Set hysteresis at 6C 0: Thermal Sensor is enabled; temperature readings are updated at sampling rate 1: Thermal Sensor is shut down; temperature reading is frozen to value recorded before SHDN 0: Critical trip register can be updated 1: Critical trip register cannot be modified; this bit can be cleared only at POR 0: Alarm trip registers can be updated 1: Alarm trip registers cannot be modified; this bit can be cleared only at POR 0: Always reads as 0 (self-clearing) 1: Writing a 1 to this position clears an event recording in interrupt mode only 0: EVENT output pin is not being asserted 1: EVENT output pin is being asserted 0: EVENT output disabled; polarity dependent: open-drain for B1 = 0; grounded for B1 = 1 1: EVENT output enabled 0: event condition triggered by alarm or critical temperature limit crossing 1: event condition triggered by critical temperature limit crossing only 0: EVENT output active low 1: EVENT output active high 0: Comparator mode 1: Interrupt mode
B8 B7 B6 B5 B4 B3 B2 B1
(5)
(4)
(4)
(3)
(2)
(1)
(7)
(1), (6)
B0
(1)
Notes: (1) Can not be altered (set or cleared) as long as either one of the two lock bits, B6 or B7 is set. (2) This bit is a polarity independent `software' copy of the EVENT pin, i.e. it is under the control of B3. (3) Writing a `1' to this bit clears an event condition in Interrupt mode, but has no effect in comparator mode. When read, this bit always returns 0. Once the measured temperature exceeds the critical limit, setting this bit has no effect (see Figure 5). (4) Cleared at power-on reset (POR). Once set, this bit can only be cleared by a POR condition. (5) The TS powers up into active mode, i.e. this bit is cleared at power-on reset (POR). When the TS is shut down the ADC is disabled and the temperature reading is frozen to the most recently recorded value. The TS can not be shut down (B8 can not be set) as long as either one of the two lock bits, B6 or B7 is set. However, the bit can be cleared at any time. (6) The output is "open-drain" and requires an external pull-up resistor for either polarity. The "natural" polarity is "active low", as it EVENT allows "wired-or" operation on the EVENT bus. (7) Can not be set as long as lock bit B6 is set.
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(c) 2010 SCILLC. All rights reserved. Characteristics subject to change without notice
CAT34TS02
HIGH LIMIT REGISTER B15 0 B7 8C B14 0 B6 4C B13 0 B5 2C B12 Sign B4 1C B11 128C B3 0.5C B10 64C B2 0.25C B9 32C B1 0 B8 16C B0 0
LOW LIMIT REGISTER B15 0 B7 8C B14 0 B6 4C B13 0 B5 2C B12 Sign B4 1C B11 128C B3 0.5C B10 64C B2 0.25C B9 32C B1 0 B8 16C B0 0
TCRIT LIMIT REGISTER B15 0 B7 8C B14 0 B6 4C B13 0 B5 2C B12 Sign B4 1C B11 128C B3 0.5C B10 64C B2 0.25C B9 32C B1 0 B8 16C B0 0
TEMPERATURE DATA REGISTER B15 TCRIT B7 8C B14 HIGH B6 4C B13 LOW B5 2C B12 Sign B4 1C B11 128C B3 0.5C B10 64C B2 0.25C* B9 32C B1 0.125C* B8 16C B0 0.0625C*
* When applicable (as defined by Capability bit TRES), unsupported bits will read as 0
Bit B15 B14 B13
Description 0: Temperature is below the TCRIT limit 1: Temperature is equal to or above the TCRIT limit 0: Temperature is equal to or below the High limit 1: Temperature is above the High limit 0: Temperature is equal to or above the Low limit 1: Temperature is below the Low limit
(c) 2010 SCILLC. All rights reserved. Characteristics subject to change without notice
17
Doc. No. MD-1129 Rev. G
CAT34TS02 REGISTER DATA FORMAT
The values used in the temperature data register and the 3 temperature trip point registers are expressed in two's complement format. The measured temperature value is expressed with 12-bit resolution, while the 3 trip temperature limits are set with 10-bit resolution. The total temperature range is arbitrarily defined as 256C, thus yielding an LSB of 0.0625C for the measured temperature and 0.25C for the 3 limit values. Bit B12 in all temperature registers represents the sign, with a `0' indicating a positive, and a `1' a negative value. In two's complement format, negative values are obtained by complementing their positive counterpart and adding a `1', so that the sum of opposite signed numbers, but of equal absolute value, adds up to zero. Note that trailing `0' bits, are `0' irrespective of polarity. Therefore the don't care bits (B1 and B0) in the 10-bit resolution temperature limit registers, are always `0'. 12-Bit Temperature Data Format Binary (B12 to B0) 1 1 1 1 0 0 0 0 0 1100 1001 0000 1100 1110 0000 1110 0111 0000 1111 1111 1111 0000 0000 0000 0000 0000 0001 0001 1001 0000 0011 0010 0000 0111 1101 0000 Hex 1C90 1CE0 1E70 1FFF 000 001 190 320 7D0 Temperature -55C -50C -25C -0.0625C 0C +0.0625C +25C +50C +125C Following a TS shut-down request, the converter is stopped and the most recently recorded temperature value present in the TDR is frozen; the EVENT output will continue to reflect the state immediatelly preceding the shut-down command. Therefore, if the state of the EVENT output creates an undesirable bus condition, appropriate action must be taken either before or after shutting down the TS. This may require clearing the event, disabling the EVENT output or perhaps changing the EVENT output polarity. In normal use, events are triggered by a change in recorded temperature, but the CAT34TS02 will also respond to limit register changes. Whereas recorded temperature values are updated at sampling rate frequency, limits can be modified at any time. The enabled EVENT output will react to limit changes as soon as the respective registers are updated.This feature may be useful during testing.
EVENT PIN FUNCTIONALITY
The EVENT output reacts to temperature changes as illustrated in Figure 14, and according to the operating mode defined by the Configuration register. In Interrupt Mode, the enabled EVENT output will be asserted every time the temperature crosses one of the alarm window limits, and can be de-asserted by writing a `1' to the clear event bit (B5) in the configuration register. When the temperature exceeds the critical limit, the event remains asserted as long as the temperature stays above the critical limit and can not be cleared. In Comparator Mode, the EVENT output is asserted outside the alarm window limits, while in Critical Temperature Mode, EVENT is asserted only above the critical limit. The exact trip limits are determined by the 3 temperature limit settings and the hystersis offsets, as illustrated in Figure 15.
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(c) 2010 SCILLC. All rights reserved. Characteristics subject to change without notice
CAT34TS02
Figure 14. Event Detail
TEMPERATURE
CRITICAL HYSTERESIS AFFECTS THESE TRIP POINTS UPPER ALARM WINDOW LOWER
S/W CLEARS EVENT EVENT IN "INTERRUPT"
TIME
EVENT IN "COMPARATOR" MODE
EVENT IN "CRITICAL TEMP ONLY" MODE
1. EVENT CANNOT BE CLEARED ONCE THE DUT TEMPERATURE IS GREATER THAN THE CRITICAL TEMPERATURE
Figure 15. Hysteresis Detail
TH
TH - HYST
TL TL - HYST
BELOW WINDOW BIT
ABOVE WINDOW BIT
(c) 2010 SCILLC. All rights reserved. Characteristics subject to change without notice
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Doc. No. MD-1129 Rev. G
CAT34TS02 PACKAGE OUTLINE DRAWING
TDFN 8-Pad 2 x 3 mm (VP2)
(1)
D
A
e
b
E
E2 PIN#1 IDENTIFICATION
A1 PIN#1 INDEX AREA D2 L
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBO L A A1 A2 A3 b D D2 E E2 e L
MIN 0.70 0.00 0.45 0.20 1.90 1.30 2.90 1.20 0.20
NOM 0.75 0.02 0.55 0.20 REF 0.25 2.00 1.40 3.00 1.30 050 TYP 0.30
MAX 0.80 0.05 0.65
A2 A3
FRONT VIEW
0.30 2.10 1.50 3.10 1.40 0.40
Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC specification MO-229.
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(c) 2010 SCILLC. All rights reserved. Characteristics subject to change without notice
CAT34TS02 EXAMPLE OF ORDERING INFORMATION (1)
Prefix
CAT
Group ID
Device # Suffix
34TS02 VP2
Package VP2: TDFN
G
T4
Tape & Reel T: Tape & Reel 4: 4,000/Reel
B
Lead Finish G: NiPdAu
Device Revision
TOP MARKING
G
1
T
2
B
3
4
5
6
7
8
Top Mark Legend 1 2 3 4 5 6 7 8
(Position) Device code "GTB".
Assembly location code
Last two digits of assembly lot number
Production year (last digit)
Production month (1 - 9, O, N, D)
Pb-free microdot
Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is NiPdAu. (3) This device used in the above example is a CAT34TS02, device revision `B' in TDFN, NiPdAu Lead Frame, Tape & Reel, 4,000/Reel.
(c) 2010 SCILLC. All rights reserved. Characteristics subject to change without notice
21
Doc. No. MD-1129 Rev. G
CAT34TS02 REVISION HISTORY
Date 06-Aug-08 15-Aug-08 04-Nov-08 20-Apr-09 Revision A B C D Description Initial Issue Update Power-On Reset, Temperature Sensor Operation and Register Change logo and fine print to ON Semiconductor Update Features, Description, Parametric Tables, TS functionality description, Ordering Information, Align to JC42.4 TSE2002av Standard terminology Updated Features Updated Parametric tables (D.C. and A.C.) Updated Bus Timing figure Added Typical Performance Characteristics Updated Capability Register content Updated Configuration Register description Updated Ordering Information Updated A.C. Characteristics table and notes Updated Capability Register description and notes Updated D.C. Operating Characteristics table Updated POR Description Updated Capability Register Updated Device ID register Updated Ordering Part Number (OPN) Updated Marking
21-Jul-09
E
2-Sep-09
F
8-June-10
G
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center: Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
Doc. No. MD-1129 Rev. G
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(c) 2010 SCILLC. All rights reserved. Characteristics subject to change without notice

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